1. Field of the Invention
This invention relates to information storage systems and particularly to systems that use a semiconductor device as the active element and a capacitor as the storage element.
2. Description of the Prior Art
Memory systems of which each storage cell is formed of but one capacitor and one active element are well known to the prior art.
U.S. Pat. No. 2,828,447, entitled, "Neon Capacitor Memory System" issued Mar. 25, 1958, to J. W. Mauchly, teaches the use of a memory storage matrix which includes memory cells comprising a capacitor and a bilateral conducting neon gas tube. Information is stored on a plurality of capacitors directly coupled to a common bit/sense line. Each gas tube acts as a threshold dependent switching element.
U.S. Pat. No. 3,196,405, entitled, "Variable Capacitance Information Storage System," issued July 20, 1965, to J. B. Gunn and assigned to the assignee of the instant invention, teaches a capacitive memory system utilizing a pair of diodes, connected front-to-back, and a capacitor to form a memory cell. Although the memory provides nondestructive readout, bipolar control signals are necessary and data inversion taken place upon readout.
U.S. Pat. No. 3,553,658, entitled, "Active Storage Array Having Diodes for Storage Elements," issued Jan. 5, 1971, to W. D. Pricer and assigned to the instant assignee, teaches the use of capacitive memory cell comprising only two back-to-back connected diodes.
The article, "Vertical Diode-Capacitor Memory Cells," W. H. Chang et al, IBM Technical Disclosure Bulletin February 1973, pages 287-9, teaches an integrated capacitive memory cell which includes a single diode and capacitor.
Both of the last two referred to memory systems utilizing diodes have the disadvantage of requiring load devices to limit the forward current and also the disadvantage of conducting at low forward voltages leading to noise problems.
U.S. Pat. No. 3,387,286, entitled, "Field Effect Transistor Memory," issued June 4, 1968 to R. H. Dennard and assigned to the present assignee, describes an array of semiconductor memory cells each comprising only a single metal oxide semiconductor enhancement mode field effect transistor (MOSFET) coupled to a storage capacitor. The MOSFET acts as a gating element and has its drain electrode connected to a bit/sense line and its gate electrode connected to a word line. The storage capacitor is coupled between the source electrode of the MOSFET and a reference potential. An inherent problem in the use of MOSFET elements in memory cells is their comparatively slow operation.
U.S. Pat. No. 3,876,992, entitled, "Bipolar Transistor Memory with Capacitive Storage," issued Apr. 8, 1975 to W. D. Pricer, and assigned to the instant assignee, discloses an integrated memory cell comprising only a single bipolar transistor and a capacitor. Although these bipolar cells have an inherently high speed than MOSFET's they have a significantly lower density because of the necessary isolation regions surrounding each cell.
Another variation in the integrated capacitive storage area is taught in U.S. Pat. No. 3,676,715, entitled, "Semiconductor apparatus for Image Sensing and Dynamic Storage," issued July, 11, 1972, to S. Brojdo, which describes the use of a PN-junction diode coupled with a depletion voltage variable capacitor as a storage element. Stored information is represented by the presence or absence of carriers in a depletion region created by a field effect gate electrode. In order to write logical 1's and 0's into the storage cell a two step operation is necessary which undesirably causes the cycle time to be extended.
Another version of the FET/capacitor memory cell is disclosed in U.S. Pat. No. 3,705,391, entitled, "Memory System Employing Capacitance Storage Means," issued Dec. 5, 1972, to R. H. Baker, which describes the use of a plurality of independently accessible FET devices serially connected through storage capacitances to a common input/output line. The memory system is organized and operates in a similar manner to that of the Dennard reference.
A depletion mode field effect transistor in which a gate is disposed in a semiconductor body surrounding a channel region, it is taught in U.S. Pat. No. 3,295,030 and its divisional companion case 3,427,212. A similar type current modulated field effect transistor is also taught in U.S. Pat. No. 3,430,113.
In summary, although numerous variations of capacitive memory storage elements have been previously disclosed, there exists certain inherent limitations in these systems which prevents their efficient application in data processing information storage systems. And while each of the above techniques utilizes only a single active switching device and a single capacitor as a memory cell to achieve maximum density, the bipolar device versions are limited somewhat in density due to the requirement of isolation regions while the FET versions are limited in their performance. The diode/capacitor memory cells utilizing avalanche breakdown present a reliability problem.